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? semiconductor components industries, llc, 2014 june, 2014 ? rev. 20 1 publication order number: nbsg16/d nbsg16 2.5 v/3.3 v?sige differential receiver/driver with rsecl* outputs *reduced swing ecl description the nbsg16 is a differential receiver/driver targeted for high frequency applications. the device is functionally equivalent to the ep16 and lvep16 devices with much higher bandwidth and lower emi capabilities. inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), hstl, lvttl, lvcmos, cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. the v bb and v mm pins are internally generated voltage supplies available to this device only. the v bb is used as a reference voltage for single-ended necl or pecl inputs and the v mm pin is used as a reference voltage for lvcmos inputs. for all single-ended input conditions, the unused complementary differential input is connected to v bb or v mm as a switching reference voltage. v bb or v mm may also rebias ac coupled inputs. when used, decouple v bb and v mm via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb and v mm outputs should be left open. features ? maximum input clock frequency > 12 ghz typical ? maximum input data rate > 12 gb/s typical ? 120 ps typical propagation delay ? 40 ps typical rise and fall times ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee =0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = ?2.375 v to ?3.465 v ? rsecl output level (400 mv peak-to-peak output), differential output only ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, and lvel devices ? v bb and v mm reference voltage output ? these are pb-free devices a = assembly location l = wafer lot y = year w = work week = pb-free package marking diagrams* qfn?16 mn suffix case 485g http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information (note: microdot may be in either location) 16 sg 16 alyw 1 ??? ???
nbsg16 http://onsemi.com 2 v ee nc nc v ee v ee v bb v mm v ee v cc q q v cc vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 nbsg16 exposed pad (ep) figure 1. qfn?16 pinout (top view) table 1. pin description pin name i/o description 1 vtd ? internal 50 termination pin. see table 2. 2 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. internal 75 k to v ee and 36.5 k to v cc . 3 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. internal 75 k to v ee 4 vtd ? internal 50 termination pin. see table 2. 5, 8, 13, 16 v ee ? negative supply voltage 6,7 nc ? no connect 9, 12 v cc ? positive supply voltage 10 q rsecl output noninverted differential output. typically terminated with 50 to v tt = v cc ? 2 v 11 q rsecl output inverted differential output. typically terminated with 50 to v tt = v cc ? 2 v 14 v mm ? lvcmos reference voltage output. (v cc ? v ee )/2 15 v bb ? ecl reference voltage output ? ep ? the exposed pad (ep) on the qfn?16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat-sinking conduit. the pad is not electrically connected to the die but may be electrically and thermally connected to v ee on the pc board. 1. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. the thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 2. in the dif ferential configuration when the input termination pins (vtd, vtd ) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
nbsg16 http://onsemi.com 3 50 50 vtd d d vtd v mm q q v bb v ee v cc figure 2. logic diagram 75 k 75 k 36.5 table 2. interfacing options interfacing options connections cml connect vtd and vtd to v cc lvds connect vtd and vtd together ac?coupled bias vtd and vtd inputs within (v ihcmr ) common mode range rsecl, pecl, necl standard ecl termination techniques lvttl the external voltage should be applied to the unused complementary differential input. nominal voltage is 1.5 v for lvttl. lvcmos v mm should be connected to the unused complementary differential input. table 3. attributes characteristics value internal input pulldown resistor (d, d ) 75 k internal input pullup resistor (d ) 36.5 k esd protection human body model machine model > 2 kv > 100 v moisture sensitivity (note 3) pb-free level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 167 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d.
nbsg16 http://onsemi.com 4 table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ?3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ?3.6 v v v inpp differential input voltage |d ? d | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v i out output current continuous surge 25 50 ma i bb v bb sink/source 1 ma i mm v mm sink/source 1 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction-to-ambient) (note 4) 0 lfpm 500 lfpm 41.6 35.2 c/w jc thermal resistance (junction-to-case) 2s2p (note 4) 4.0 c/w t sol wave solder pb-free 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 powe r) with 8 filled thermal vias under exposed pad.
nbsg16 http://onsemi.com 5 table 5. dc characteristics, input with rspecl output (v cc = 2.5 v; v ee = 0 v) (note 5) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max power supply current i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma rspecl outputs (note 6) v oh output high voltage 1450 1530 1575 1525 1565 1600 1550 1590 1625 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv differential clock inputs driven single-ended (figures 5 & 7) (note 7) v ih input high voltage 1200 v cc 1200 v cc 1200 v cc mv v il input low voltage 0 v ih ? 150 0 v ih ? 150 0 v ih ? 150 mv v th input threshold voltage range (note 8) 950 v cc ? 75 950 v cc ? 75 950 v cc ? 75 mv v ise single-ended input voltage (v ih ? v il ) 150 2600 150 2600 150 260 mv v bb pecl output voltage reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mv differential inputs driven differentially (figures 6 & 8) (note 9) v ihd differential input high voltage 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage 0 v ihd ? 75 0 v ihd ? 75 0 v ihd ? 75 mv v id differential input voltage (v ihd ? v ild ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (note 10) (figure 9) 1200 2500 1200 2500 1200 2500 mv i ih input high current (@v ih ) 30 100 30 100 30 100 a i il input low current (@v il ) 25 50 25 50 25 50 a lvcmos control pin v mm cmos output voltage reference v cc /2 1100 1250 1400 1100 1250 1400 1100 1250 1400 mv termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. all loading with 50 to v cc ? 2.0 v. 7. v th , v ih , v il, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single-ended mode. v th = (v ih ? v il ) / 2. 9. v ihd , v ild, v id and v ihcmr parameters must be complied with simultaneously. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nbsg16 http://onsemi.com 6 table 6. dc characteristics, input with rspecl output (v cc = 3.3 v; v ee = 0 v) (note 11) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max power supply current i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma rspecl outputs (note 12) v oh output high voltage 2250 2330 2375 2325 2365 2400 2350 2390 2425 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv differential clock inputs driven single-ended (figures 5 & 7) (note 13) v ih input high voltage 1200 v cc 1200 v cc 1200 v cc mv v il input low voltage 0 v ih ? 150 0 v ih ? 150 0 v ih ? 150 mv v th input threshold voltage range (note 14) 950 v cc ? 75 950 v cc ? 75 950 v cc ? 75 mv v ise single-ended input voltage (v ih ? v il ) 150 2600 150 2600 150 260 mv v bb pecl output voltage reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mv differential inputs driven differentially (figures 6 & 8) (note 15) v ihd differential input high voltage 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage 0 v ihd ? 75 0 v ihd ? 75 0 v ihd ? 75 mv v id differential input voltage (v ihd ? v ild ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (note 16) (figure 9) 1200 3300 1200 3300 1200 3300 mv i ih input high current (@v ih ) 30 100 30 100 30 100 a i il input low current (@v il ) 25 50 25 50 25 50 a lvcmos control pin v mm cmos output voltage reference v cc /2 1500 1650 1800 1500 1650 1800 1500 1650 1800 mv termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. input and output parameters vary 1:1 with v cc . 12. all loading with 50 to v cc ? 2.0 v. 13. v th , v ih , v il, and v ise parameters must be complied with simultaneously. 14. v th is applied to the complementary input when operating in single-ended mode. v th = (v ih ? v il ) / 2. 15. v ihd , v ild, v id and v ihcmr parameters must be complied with simultaneously. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nbsg16 http://onsemi.com 7 table 7. dc characteristics, necl or rsnecl input with necl output (v cc = 0 v; v ee = ?3.465 v to ?2.375 v) (note 17) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max power supply current i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma rspecl outputs (note 18) v oh output high voltage ?1050 ?970 ?925 ?975 ?935 ?900 ?950 ?910 ?875 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv differential clock inputs driven single-ended (figures 5 & 7) (note 19) v ih input high voltage v ee + 1200 v cc v ee + 1200 v cc v ee + 1200 v cc mv v il input low voltage v ee v ih ? 150 v ee v ih ? 150 v ee v ih ? 150 mv v th input threshold voltage range (note 20) v ee + 950 v cc ? 75 v ee + 950 v cc ? 75 v ee + 950 v cc ? 75 mv v ise single-ended input voltage (v ih ? v il ) 150 2600 150 2600 150 260 mv v bb necl output voltage reference ?1420 ?1360 ?1300 ?1420 ?1360 ?1300 ?1420 ?1360 ?1300 mv differential inputs driven differentially (figures 6 & 8) (note 21) v ihd differential input high voltage v ee + 1200 v cc v ee + 1200 v cc v ee + 1200 v cc mv v ild differential input low voltage v ee v ihd ? 75 v ee v ihd ? 75 v ee v ihd ? 75 mv v id differential input voltage (v ihd ? v ild ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (note 22) (figure 9) v ee + 1200 0 v ee + 1200 0 v ee + 1200 0 mv i ih input high current (@v ih ) 30 100 30 100 30 100 a i il input low current (@v il ) 25 50 25 50 25 50 a lvcmos control pin (note 23) v mm cmos output voltage reference v cc /2 v mm ? 150 v mm v mm + 150 v mm ? 150 v mm v mm + 150 v mm ? 150 v mm v mm + 150 mv termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. input and output parameters vary 1:1 with v cc . 18. all loading with 50 to v cc ? 2.0 v. 19. v th , v ih , v il, and v ise parameters must be complied with simultaneously. 20. v th is applied to the complementary input when operating in single-ended mode. v th = (v ih ? v il ) / 2. 21. v ihd , v ild, v id and v ihcmr parameters must be complied with simultaneously. 22. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 23. v mm typical = |v cc ? v ee |/2 + v ee = v mmt
nbsg16 http://onsemi.com 8 table 8. ac characteristics (v cc = 0 v; v ee = ?3.465 v to ?2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum input clock frequency (see figure 3. f max /jitter) (note 24) 10.7 12 10.7 12 10.7 12 ghz t plh , t phl propagation delay to output differential 90 110 130 100 120 140 95 125 145 ps t skew duty cycle skew (note 25) 3 15 3 15 3 15 ps t jitter rms random clock jitter f in < 10 ghz peak?to?peak data dependent jitter f in < 10 gb/s 0.2 8 2 0.2 8 2 0.2 8 2 ps v inpp input voltage swing/sensitivity (differential configuration) (note 26) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 20 30 50 20 30 50 20 30 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. measured using a 400 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 25. see figure 10. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 26. v inpp(max) cannot exceed v cc ? v ee
nbsg16 http://onsemi.com 9 output amp rms jitter input frequency (ghz) figure 3. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at ambient temperature (typical) output voltage amplitude (mv) jitter out ps (rms) 700 600 500 400 300 200 100 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9.5 8.5 7.5 6.5 3.5 2.5 5.5 4.5 0.5 ?0.5 1.5 q q figure 4. 10.709 gb/s diagram (3.0 v, 25 c) x = 17ps/div y = 70 mv/div
nbsg16 http://onsemi.com 10 in v th in v th figure 5. differential input driven single-ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin v ee v th in in v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v ihcmr v ee v id = v ihd ? v ild v cc v ihd v ild v id = |v ihd(in) ? v ild(in )| in in figure 6. differential inputs driven differentially figure 7. v th diagram figure 8. differential inputs driven differentially figure 9. v ihcmr diagram in in v ihcmrmax v ihcmrmin in
nbsg16 http://onsemi.com 11 figure 10. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) figure 11. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? nbsg16mng qfn-16 (pb-free / halide-free) 123 units / tube nbsg16mnr2g qfn-16 (pb-free / halide-free) 3000 / tape & reel NBSG16MNHTBG qfn-16 (pb-free / halide-free) 100 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nbsg16 http://onsemi.com 12 package dimensions qfn16 3x3, 0.5p case 485g issue f ??? ??? ??? ??? 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distribut ors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nbsg16/d the products described herein (nbsg16), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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